Hi Bob, I enjoy following your progress in your hard and software designs and I noticed that in V5.0 you have left off the 10uf cap on barrel side of the Voltage jack that you had in all your previous PCB versions.
Any reason for that?
Regards,
Gustave
That cap was left over from the original design before an op-amp was added to provide a low-impedance bias. It was needed to run the ADCs at full speed. The cap was adding a lot of phase shift to the VT signal, so since I was adding two more VT inputs, I decided to bite the bullet and remove it so all three would be the same.
Just prior to this hardware rev, the firmware was modified to allow more robust phase correction. So now the firmware can compensate for the cap phase shift in the older hardware, which varies with frequency, while using the lower shift in the V5.
The current batch of V4 are a hybrid that uses the V5 board without the cap but no additional VT inputs. The version and board specifics are configured in the ESP EEPROM during manufacture.
Thanks. Makes sense. Any plans to put the V5 PCB Schedule on Github?
I’ll get around to it.